library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity int_to_hex is
	port (
		Int: in std_logic_vector(0 to 3) := "0000";
		HexOut: out std_logic_vector(0 to 6) := "0000000"
	);		
end;


architecture rtl of int_to_hex is
begin
	process(Int)
		variable vals : integer;
	begin
		vals := to_integer(unsigned(Int));
		case vals is
		when 0 => HexOut <= "0000001";
		when 1 => HexOut <= "1001111";
		when 2 => HexOut <= "0010010";
		when 3 => HexOut <= "0000110";
		when 4 => HexOut <= "1001100";
		when 5 => HexOut <= "0100100";
		when 6 => HexOut <= "0100000";
		when 7 => HexOut <= "0001111";
		when 8 => HexOut <= "0000000";
		when 9 => HexOut <= "0000100";
		when 10 => HexOut <= "0001000";
		when 11 => HexOut <= "1100000";
		when 12 => HexOut <= "0110001";
		when 13 => HexOut <= "1000010";
		when 14 => HexOut <= "0110000";
		when 15 => HexOut <= "0111000";
		when others => HexOut <= "1111111"; -- all off
		end case;
	end process;
end;